Conference Program

Facing the Multicore-Challenge II

September 28-30, 2011
Karlsruhe Institute of Technology

Wednesday, September 28, 2011

09:30h - 10:15h	Registration and Coffee
10:15h - 10:30h	Welcome and Opening
10:30h - 11:30h	Invited Talk  Only the First Steps of the Parallel Evolution have been taken thus far  James R. Reinders, Intel
11:30h - 11:55h	Paper   Performance and Productivity of New Programming Languages   Iris Christadler, Giovanni Erbacci, Alan D. Simpson
11:55h - 12:20h	Paper   Towards high-performance implementations of a custom HPC kernel using Intel Array Building Blocks   Alexander Heinecke, Michael Klemm, Hans Pabst, Dirk Pflüger

12:20h-13:30h

Lunch Break

13:30h - 13:55h	Paper       AHDAM: an Asymmetric Homogeneous with Dynamic Allocation Manycore Chip                                             Charly Bechara, Nicolas Ventroux, Daniel Etiemble
13:55h - 14:20h	Paper  FPGA Implementation of the Robust Essential Matrix Estimation with RANSAC                                      and the 8-point and the 5-point Method  Michał Fularz, Marek Kraft, Adam Schmidt, Andrzej Kasiński
14:20h - 15:10h	Short Talks I   Verifying Programs on Relaxed Memory Models    Alexander Linden  Modeling Performance through Memory-Stalls  Roman Iakymchuk  Efficient Serial and Parallel Coordinate Descent Methods for Huge-Scale Convex Optimization  Martin Takac  Interval Arithmetic for Graphic Processors  Marko Nehmeier
15:10h - 15:45h	Coffee Break
15:45h - 17:45h	Tutorial  The SMPSs Programming Model  Marta Garcia, Barcelona Supercomputing Centre, Spain                                  Rainer Keller, HLRS, Stuttgart, Germany

19:30h - 22:00h

Conference Dinner Badisch Brauhaus

Thursday, September 29, 2011

09:00h -  10:00h	Invited Talk  Balance principles for algorithm-architecture co-design                                  Richard Vuduc, Georgia Institute of Technology, USA
10:00h -  10:25h	Paper  Hybrid Parallelization of a Realistic Heart Model  Dorian Krause, Mark Potse, Thomas Dickopf, Rolf Krause, Angelo Auricchio, Frits Prinzen
10:25h - 10:50h	Paper  Using Free Scheduling for Programming NVIDIA Cards  Wlodzimierz Bielecki, Marek Palkowski
10:50h - 11:20h	Coffee Break and Poster Session
11:20h - 13:00h	Tutorial  Principles of Multicore Optimization  Jan Treibig, RRZE Erlangen, Germany

13:00h-14:00h

Lunch Break

14:00h - 14:25h	Paper  GPU Accelerated Computation of the Longest Common Subsequence  Katsuya Kawanami, Noriyuki Fujimoto
14:25h - 14:50h	Paper  Experiences with High-Level Programming Directives for Porting Applications to GPUs                                         Oscar Hernandez, Wei Ding, Barbara Chapman, Ramanan Sankaran, Richard Graham, Christos Kartsaklis
14:50h - 15:15h	Paper  A GPU Algorithm for Greedy Graph Matching  B. O. Fagginger Auer, R. H. Bisseling
15:15h - 15:45h	Coffee Break and Poster Session
15:45h - 17:15h	Tutorial  Unleash the Power of Modern CPUs through Vectorization and Parallelization  Hans Pabst, Intel

18:00h - 20:00h

Social Event: ZKM Car Culture

 

09:00h - 09:25h	Paper  Efficient AMG on Heterogeneous Systems  Jiri Kraus, Malte Förster
09:25h - 09:50h	Paper  A GPU-Accelerated Parallel Preconditioner for the Solution of the  Boltzmann Transport Equation for Semiconductors  Karl Rupp, Ansgar Jüngel, Tibor Grasser
09:50h - 10:15h	Paper  Parallel Smoothers for Matrix-based Geometric Multigrid Methods on Locally Refined Meshes                                 Using Multicore CPUs and GPUs  Vincent Heuveline, Dimitar Lukarski, Nico Trost, Jan-Philipp Weiss
10:15h - 10:45h	Coffee Break and Poster Session
10:45h - 11:35h	Short Talks II (4 Talks)  Effects of 3-D Stacked Vector Cache on Energy Consumption  Ryusuke Egawa  Latency Reduction in Parallel Streaming Applications  Sebastian Mattheis  Communication Efficiency in ProActive  Marek Nowicki  Towards Efficient Two-Level Preconditoned Conjugate Gradient on the GPU  Rohit Gupta
11:35h - 12:45h	Panel Discussion  Where does Manycore Lead Us? Where are we now?

12:45h - 13:45h

Lunch Break

13:45h - 14:35h

Short Talks III  The symbolic manipulation system FORM and its parallelization  Takahiro Ueda  Evaluation of maximum likelihood fits on GPU devices using CUDA  Felice Pantaleo  Employing a High-Level Language for Porting Numerical Applications to Reconfigurable Hardware               Mareike Schmidtobreick       Analysis of Event Processing Design Patterns and their Performance Dependency  on I/O Notification  Mechanisms  Ronald Strebelow

14:35h - 14:45h

Wrap-Up and Closing

	Overview of Posters
	Two Level Preconditioned CG Method on the GPU Rohit Gupta A GPU Parallel Coordinate Descent Method for Large-Scale Truss Topology Design Martin Takac Verifying Programs on Relaxed Memory Models Alexander Linden